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High-bandwidth memory stacking yield

Stacking memory chips next to a processor without breaking them. Three companies can do it at volume.

The bottleneck itself →

Searched for “high bandwidth memory”, “hybrid bonding”, “through-silicon via”, “DRAM stacking” in titles and abstracts.

1 collected items, newest first ↓Judged by hand ↓Who is active ↓

All stagesFundamental researchApplied / labPilot / demonstrationEarly commercialAt scaleNewestMost cited

Pilot / demonstration — readiness 5 to 7 of the nine-point scale. Evidence it takes: A pilot line, field trial or demonstration announced by the organisation running it; a demonstration or SBIR Phase II grant.

Judged by hand

Readiness and substitute status, with reasoning
  • TechnologyPilot / demonstrationreadiness Estimate, not a measurementIn production for some image sensors and logic stacks; ramping for memory stacks.By Substrata, open to challenge · 2026-09-15Supporting source →Judgement, cited · 2026-09-15

    Hybrid bonding

    In production for some image sensors and logic stacks; ramping for memory stacks.

    Source ↗

Collected by the feeds

Newest first
  • GrantUS National Science FoundationSTTR Phase IISourcedNSF awardsOpen the source →

    STTR Phase II: Miniature Precision Stage for High Throughput Hybrid Bonding

    The broader/commercial impact of this Small Business Technology Transfer (STTR) Phase II project is to develop a small form-factor precision stage to enable the high-volume manufacturing of next generation high-performance computing devices utilizing 3D stacked chiplets…

    SANGTERA INC

    Pilot / demonstration · SBIR/STTR Phase II award.From NSF awards · not yet reviewed