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AI & compute · Semiconductors

Hybrid bonding

Joining two chips copper-to-copper with no bumps between them, so they behave more like one piece of silicon.

Readiness · Estimate, not a measurementIn production for some image sensors and logic stacks; ramping for memory stacks.By Substrata, open to challenge · 2026-09-15Supporting source → — Pilot running in the real environment (Being proven)Report an error on GitHub

01What it would relieve

  • High-bandwidth memory stacking yieldHow this is computedSum of four judged scores, each 0–3: concentration + substitution + lead time + inelasticity.Method →Code →

    Removes the bump layer that limits how many memory dies can be stacked and cooled.

  • Advanced packaging capacityHow this is computedSum of four judged scores, each 0–3: concentration + substitution + lead time + inelasticity.Method →Code →

    More function per package reduces how much packaging capacity a given amount of compute needs.

02How far off it is

judged 2026-09-15

7 / 9Pilot running in the real environment

In production for some image sensors and logic stacks; ramping for memory stacks.

Source ↗

03What to watch for

A memory generation shipping in volume on hybrid bonding.

04Who and what it would touch

each join carries its own evidence

High-bandwidth memory stacking yield

Companies that make it today

sourced

Other science aimed at it
Nothing else is on record yet.
Who could fund relief
No funder is on record yet.
Where it comes from

directory join, not a sourced finding

What it holds up

the project's own model, not a measurement

Advanced packaging capacity

Companies that make it today

sourced

What depends on it

primary source

Other science aimed at it
Nothing else is on record yet.
Who could fund relief
No funder is on record yet.
Where it comes from

directory join, not a sourced finding

What it holds up

the project's own model, not a measurement

05What this holds up

4 loops
  • Software scaffoldone turn: Minutes

    would relieve High-bandwidth memory stacking yield, which gates it.

    Worst judgement on this loop: How this is computedThe highest severity score among the bottlenecks recorded as gates on the loop.Method →Code →, judged 2026-09-15 · this join is source-backed readiness judgement

  • Frontier training runone turn: Weeks to months

    would relieve High-bandwidth memory stacking yield, which gates it.

    Worst judgement on this loop: How this is computedThe highest severity score among the bottlenecks recorded as gates on the loop.Method →Code →, judged 2026-09-15 · this join is source-backed readiness judgement

  • Software scaffoldone turn: Minutes

    would relieve Advanced packaging capacity, which gates it.

    Worst judgement on this loop: How this is computedThe highest severity score among the bottlenecks recorded as gates on the loop.Method →Code →, judged 2026-09-15 · this join is source-backed readiness judgement

  • Frontier training runone turn: Weeks to months

    would relieve Advanced packaging capacity, which gates it.

    Worst judgement on this loop: How this is computedThe highest severity score among the bottlenecks recorded as gates on the loop.Method →Code →, judged 2026-09-15 · this join is source-backed readiness judgement

A loop is one design, build and measure turn. Severity is a dated judgement on a 0–12 scale, not a measurement, and the judgements are not added together — the figure shown is the worst single one.

Discussion

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