Advanced packaging capacity
Assembling several chips into one AI accelerator. How many exist is set here, not at the wafer.
judged, with a citation claimed, no citationNumber: papers, preprints and grants the feeds collected — unreviewed
Searched for “advanced packaging”, “chiplet”, “silicon interposer”, “fan-out wafer level” in titles and abstracts.
78 collected items, newest first ↓Judged by hand ↓Who is active ↓
All stagesFundamental researchApplied / labPilot / demonstrationEarly commercialAt scaleNewestMost cited
Directory companies in this research
- MicronMU US2 (Computed: Items per institution per bottleneck, counting each item once per institution named on it by the source; a company is matched to the directory only when every distinguishing word of both names agrees.) itemslatest 2026-09-15
- IntelINTC USvia Intel1 (Computed: Items per institution per bottleneck, counting each item once per institution named on it by the source; a company is matched to the directory only when every distinguishing word of both names agrees.) itemlatest 2022-09-01
Named on a collected paper or grant, matched to the directory by the strict name rule. A company not in the directory, or spelled differently by the source, is not shown here.
Judged by hand
- Hybrid bonding
In production for some image sensors and logic stacks; ramping for memory stacks.
Collected by the feeds
- Network-on-Chip Technology for Chiplet Integration Architecture
In today's era, the marginal benefits of transistor scaling are continuously decreasing, and Chiplet heterogeneous integration has become the mainstream path for scaling AI chip computing power. Meanwhile, on-chip interconnect performance is increasingly becoming the key factor…
Fundamental research · No laboratory or pilot wording.From OpenAlex · not yet reviewedDOI
- MICROSOFT MAIA 300 // N2P MULTI-CHIPLET // 288GB HBM4.
MICROSOFT MAIA 300 // N2P MULTI-CHIPLET // 288GB HBM4.
Fundamental research · No laboratory or pilot wording.From OpenAlex · not yet reviewedDOI
- Recent Advances in Performance-Driven Multiscale Strategies for Epoxy-Based Underfill Materials for Advanced Packaging
The rapid evolution of advanced packaging toward high-density, high-power, and three-dimensional heterogeneous integration has placed increasingly stringent demands on package reliability, particularly because of the thermal expansion mismatch and associated thermomechanical…
Key Laboratory of Functional Materials and Applications of Fujian ProvinceXiamen University of Technology
Fundamental research · No laboratory or pilot wording.From OpenAlex · not yet reviewedDOI
- Semantic D2D Gateway Firewalls for Multi-Tenant Chiplet NoC Resource Isolation
Fundamental research · No laboratory or pilot wording.From OpenAlex · not yet reviewedDOIPDF
- A Bandwidth-Balanced Adaptive Technique for Mesh-Based I/O Chiplets
As the semiconductor industry rapidly embraces chiplet-based architectures to satisfy AI-driven high-performance computing demands, the flexible, scalable I/O‑Die (IOD) chiplet offers a promising path toward solving the AI memory wall. However, the design of these IOD chiplets…
American Rock Mechanics Association
Fundamental research · No laboratory or pilot wording.From OpenAlex · not yet reviewedDOIPDF
- Solid‐Liquid Interdiffusion Bonding Enabling Heterogeneous Integration on Flexible and Shapeable Polymer Platforms
The integration of rigid microscale electronics onto soft and flexible polymer substrates remains a key challenge for flexible electronics, biointegrated systems, and body-first microrobotics, where the mechanical body, material architecture, morphology, and primary functions are…
Chemnitz University of Technology
Applied / lab · Says "fabricated".From OpenAlex · not yet reviewedDOI
- Mode Purity Beyond Conductor Count: Miniature Sommerfeld–Goubau Interconnects and Their Engineering Envelope in Advanced Packaging
This preprint proposes Mode Purity Beyond Conductor Count, investigating whether miniature Sommerfeld–Goubau (μ-Goubau) or SSPP slow-wave structures can sustain bound guided-wave propagation inside packaging-scale micro-environments. It constructs an eight-dimensional…
Fundamental research · No laboratory or pilot wording.From OpenAlex · not yet reviewedDOIalso at doi.orgalso at doi.org
- Terahertz nondestructive evaluation of heterogeneous packaging stackup: Multi-layer interposer
With increasing integration density of semiconductor devices, high-speed interconnects and advanced packaging techniques are essential to meet the growing demands of artificial intelligence and large-scale computing. Three-dimensional packaging, where multiple chips are stacked…
Georgia Tech-EuropeCentre National de la Recherche ScientifiqueGeorgia Institute of Technology
Fundamental research · No laboratory or pilot wording.From OpenAlex · not yet reviewedDOIPDF
- Boundary-Defined Power Integrity: Spatial Energy Flow, Mutual-Inductance Topology, and Cavity-Mode Control in Mid-to-High-Frequency PDNs
This preprint establishes Boundary-Defined Power Integrity for mid-to-high-frequency power distribution networks in AI accelerators, Chiplets, and advanced packaging. It reframes the PDN as a spatial energy-flow and relational-closure problem rather than a one-dimensional…
Fundamental research · No laboratory or pilot wording.From OpenAlex · not yet reviewedDOIalso at doi.orgalso at doi.org
- AI-Based Image Enhancement Improves Detection of Interconnect Defects in Microelectronic Packaging
Abstract Traditional failure-analysis (FA) methods face growing challenges due to the increasing miniaturization and complexity of modern semiconductor devices. In particular, the detection of cracks in the extreme low K layers of flip-chips, utilized in advanced packaging…
Materials Center Leoben (Austria)PVA TePla (Germany)Advanced Semiconductor Engineering (Taiwan)
Fundamental research · No laboratory or pilot wording.From OpenAlex · not yet reviewedDOIPDF
- Review: diamond heterogeneous integration for thermal management—integration strategies and advanced packaging
Fundamental research · No laboratory or pilot wording.From OpenAlex · not yet reviewedDOI
- VLSI Research Articles: Hardware Security, Chiplets, In-Memory Computing, Quantum Hardware and Secure Verification
This project presents a collection of five concise technical articles covering selected topics in modern VLSI design and hardware security. The collection discusses hardware security across the VLSI design flow, chiplet-based VLSI architecture and security, SRAM-based in-memory…
Fundamental research · No laboratory or pilot wording.From OpenAlex · not yet reviewed
- Variation-Aware Thermal Design for Advanced Packaging
Thermal design of flip-chip, 2.5D and 3D packages uses nominal values of features—bond line thickness, voids, coverage, warpage, die thickness, bonded-interface conductance—that are manufactured outcomes with unit-to-unit distributions. This systematic review, conducted to a…
University of Tennessee at Knoxville
Fundamental research · No laboratory or pilot wording.From OpenAlex · not yet reviewedDOIPDF
- Chiplet-Based VLSI Design: Architecture and Hardware Security Challenges
Fundamental research · No laboratory or pilot wording.From OpenAlex · not yet reviewedDOI
- Performance Evaluation of a Silicon Interposer–Based Photodetector Module
Fundamental research · No laboratory or pilot wording.From OpenAlex · not yet reviewedDOI
- A Composable AI-Accelerated Iterative Solver for 3D-IC Thermal Modeling
Accurate thermal analysis of heterogeneous 2.5D/3D-IC packages is essential yet computationally prohibitive. A single full-package FEM simulation can take hours, while AI-based surrogates treat the entire stack as a monolithic prediction target and must be retrained whenever the…
Fundamental research · No laboratory or pilot wording.From arXiv · not yet reviewedPDFalso at doi.org
- Addition of a methylene spacer in a thiol interlayer enhances the adhesion between copper and epoxy for advanced packaging
Fudan UniversityCollaborative Innovation Center of Chemistry for Energy Materials
Fundamental research · No laboratory or pilot wording.From OpenAlex · not yet reviewedDOI
- SOMA: A Scalable Optical Memory Access Architecture for Multi-Chiplet Systems
Fundamental research · No laboratory or pilot wording.From OpenAlex · not yet reviewedDOI
- QBX: A Compiler for 2-local Qubit Hamiltonian Simulation on Quantum Chiplets
2-local qubit Hamiltonian simulation, a fundamental task in quantum computing, is widely applied in various applications. This paper presents QBX, the first quantum compiler designed for 2-local qubit Hamiltonian simulation on quantum chiplet architectures. Existing…
Fundamental research · No laboratory or pilot wording.From arXiv · not yet reviewedPDFalso at doi.org
- Nanoparticle-engineered low-temperature solders for advanced heterogeneous electronic packaging
Advanced heterogeneous packages need solder interconnects that can be assembled at lower temperature without losing mechanical, interfacial, or electrical stability. Sn–Bi and In-containing low-temperature solders (LTSs) reduce reflow-induced warpage, but brittle phase…
Fundamental research · No laboratory or pilot wording.From OpenAlex · not yet reviewedDOI
- Physically Separate, Logically Unified: A System Architecture for Composable Heterogeneous Chiplets
This work proposes a system-level architecture in which physically separate heterogeneous chiplets—CPUs, GPUs, NPUs, DSPs, FPGAs, and other accelerators—are treated as one logically unified computing environment. Computation is represented as tasks; a global scheduler selects…
Fundamental research · No laboratory or pilot wording.From OpenAlex · not yet reviewedDOIalso at doi.org
- U-Can-Inject-Errors (UCIe): A Protocol-Aware Hardware Trojan for FPGA Chiplet Links
Chiplet integration enables designers to assemble dies from multiple vendors and connect them through standardized interconnect protocols, such as universal chiplet interconnect express (UCIe). This multi-vendor model, however, redraws the trust boundary and exposes inter-chiplet…
Fundamental research · No laboratory or pilot wording.From OpenAlex · not yet reviewedDOI
- Toward Multi-kW Power Delivery Methodologies for Advanced 3D Heterogeneous Integration
The demands of modern applications require the construction of ever more complex integrated systems, with AI applications in particular serving as a significant driver for increased system size, potentially going beyond the trilliontransistor mark. The path to building these…
Fundamental research · No laboratory or pilot wording.From OpenAlex · not yet reviewedDOIPDFalso at arxiv.org
- Glass Packaging for Chiplets Heterogeneous Integration
In this study, glass packaging for chiplets heterogeneous integration has been presented. Emphasis has been placed on the applications of glass packaging to high-performance computing (HPC) and data centers driven by artificial intelligence (AI). Key topics such as organic-core…
Micron Corporation (United States)Micron in the directoryMU US
Fundamental research · No laboratory or pilot wording.From OpenAlex · not yet reviewedDOIPDF
- Cu-Cu Hybrid Bonding for Chiplets Heterogeneous Integration
Cu-Cu hybrid bonding is an old packaging technology. It has been in high volume manufacturing (HVM) for more than 10 years. In this study, HVM or to be in HVM products and potential new products with Cu-Cu hybrid bonding will be briefly mentioned. Some recommendations will be…
Micron Corporation (United States)Micron in the directoryMU US
Fundamental research · No laboratory or pilot wording.From OpenAlex · not yet reviewedDOIPDF
- Location-Aware Caching Mechanism for minimizing performance degradation induced by inefficient inter-chiplet data path
Fundamental research · No laboratory or pilot wording.From OpenAlex · not yet reviewedDOI
- Power-thermal modeling and management of modern chiplet-based processors
As semiconductor scaling approaches the limits of monolithic integration, chiplet-based architectures have become a key enabler of continued performance and energy-efficiency improvements in high-performance computing (HPC) processors. By partitioning large dies into smaller…
Fundamental research · No laboratory or pilot wording.From OpenAlex · not yet reviewedDOIPDF
- A Unified Interconnection Network for Chiplet-Based Scaling of the BrainScaleS Neuromorphic System
The BrainScaleS-2 (BSS-2) neuromorphic architecture combines analog emulation of spiking neural network (SNN) primitives with tightly coupled ADCs and digital processing units. These analog SNN primitives are fixed hardware resources that cannot be multiplexed, limiting the…
Fundamental research · No laboratory or pilot wording.From OpenAlex · not yet reviewedDOIPDFalso at doi.orgalso at arxiv.org
- Innovative Material Reinforcement Strategies for Advanced Packaging Solutions in Automotive Electronics
The growing integration of larger Ball Grid Arrays (BGAs), ceramic packages, and Wafer-Level Chip Scale Packages (WLCSPs) into automotive and other harsh-environment electronic systems necessitates enhanced reliability in printed circuit board (PCB) assemblies. These demanding…
Alpha Environmental (United States)
Fundamental research · No laboratory or pilot wording.From OpenAlex · not yet reviewedDOIPDF
- Fengshui: Demystifying Chiplet Ecosystem and Bespoke Neural Network Accelerator Codesign
Modern ML workloads, with stringent latency and energy constraints, are increasingly hard to run efficiently on homogeneous commodity hardware. We argue that operator-level disaggregation--tailoring microarchitecture, batching, and memory hierarchy to each operator--is essential…
Fundamental research · No laboratory or pilot wording.From arXiv · not yet reviewedPDFalso at doi.org
- Integration and Packaging
In beyond-CMOS nanoelectronics, integration and packaging strive for true unity in diversity, blending unconventional, non-silicon materials with classic Si-CMOS technology. This fusion seeks the creation of high-performance, compact, and highly specialized systems. By…
Fundamental research · No laboratory or pilot wording.From OpenAlex · not yet reviewedDOI
- Hardware Trojan Threats to Multi-Chiplet Photonic Neural Network Accelerators
Multi-chiplet photonic neural network accelerators (MCPNAs) combine photonic computation, photonic communica-tion, and heterogeneous chiplet integration to enable scalable and energy-efficient AI acceleration. However, their distributed archi-tecture and reliance on third-party…
Fundamental research · No laboratory or pilot wording.From arXiv · not yet reviewedPDF
- A Time-Encoded Analog Photonic Interposer for Energy-EfficientIntegration of Analog Vision Sensors and Analog Accelerators
This work introduces a time-encoded analog photonic interposer that enables long-distance, high-fidelity transport of analog signals between spatially separated chiplets. Unlike prior silicon-photonic links limited to digital data, the interposer preserves analog information by…
Fundamental research · No laboratory or pilot wording.From arXiv · not yet reviewedPDF
- Beacon: LLM Multi-Agent Driven Hardware Design Space Exploration for Heterogeneous Multi-Chiplet Deep Learning Accelerators
Heterogeneous multi-chiplet accelerators allow chiplets to be configured independently to better match different operator characteristics and improve inference efficiency. However, heterogeneity makes simulator evaluation expensive, limiting the number of iterations affordable…
Fundamental research · No laboratory or pilot wording.From arXiv · not yet reviewedPDF
- CHIPSMORE: Compute-in-Interconnect and -Memory Chiplets for Multi-Mode Multi-Request LLM Inference Acceleration
Large language model (LLM) inference exhibits substantial variability across adaptation modes, context lengths, and request concurrency, creating challenges for maintaining high utilization, memory efficiency, and scalable performance on compute-in-memory (CIM) accelerators. This…
Fundamental research · No laboratory or pilot wording.From arXiv · not yet reviewedPDF
- Generative Design of Liquid-Cooling Channels for Thermal Management of 2.5D and 3D Integrated Advanced Packaging
High-power multi-chip packages require increasingly effective cooling as intensive heat is generated within a limited package area. This work presents a physics-guided generative design framework for liquid-cooling channel topology optimization in a 2.7 kW multi-chip package…
Fundamental research · No laboratory or pilot wording.From arXiv · not yet reviewedPDF
- SBIR Fast-Track: Advanced Hexagonal Boron Nitride Composite Semiconductor Packaging for Enhanced Performance, Efficiency, and Protection
The broader/commercial impact of this Small Business Innovation Research (SBIR) Fast-Track project is the development of advanced thermally conductive and electrically insulating materials to improve the energy efficiency, performance, and reliability of next-generation…
Fundamental research · Research grant.From NSF awards · not yet reviewed
- HYDRA: A Heterogeneous Chiplet DSE Framework for Serving Dynamic Hybrid LLM Workloads
Hybrid Transformer-Mamba large language models (LLMs) enhance long-context efficiency, but their heterogeneous computation and communication patterns complicate efficient hardware acceleration. Chiplet-based architectures offer a scalable solution by integrating specialized…
Fundamental research · No laboratory or pilot wording.From arXiv · not yet reviewedPDF
- ReVolt: Power Delivery Network-Aware Voltage Droop Control for 2.5D PIM Chiplet Architectures
Processing-in-memory (PIM)-based 2.5D multi-chiplet platforms are enablers for machine learning (ML) workloads. However, their performance is affected by the power delivery network (PDN), where varying chiplet-level current demand induces spatially and temporally varying voltage…
Fundamental research · No laboratory or pilot wording.From arXiv · not yet reviewedPDF
- Hardware Design and Security in the Era of Chiplets and LLMs
The semiconductor industry is undergoing a dual revolution: the shift toward heterogeneous 2.5D chiplet systems and the integration of Large Language Models (LLMs) into Electronic Design Automation (EDA) flows. While these paradigms offer unprecedented benefits in yield…
Fundamental research · No laboratory or pilot wording.From arXiv · not yet reviewedPDF
- New award - virginia polytechnic institute and state university
control number: 3499-1536
project title: ''dual-use converter-in-fluid integrated vertical-stack kilo-ampere sic submodule
valve for next generation high-density hvdc converter station''
high-voltage direct current (hvdc) power transmission is crucial for delivering electricity
efficiently over long distances. however, current hvdc converter stations are large, expensive, and
inefficient. this project proposes a revolutionary approach to significantly reduce the size and
cost of these stations while improving their efficiency. our team will develop a novel medium-
voltage (mv) silicon carbide (sic)-based submodule valve, designed to replace conventional hvdc
power electronics with a more compact and efficient solution. the key innovations include:
high-density sic power modules these advanced modules will enable a 10 reduction in power loss
compared to existing technology, improving energy efficiency.
dual-use converter in dielectric fluid technology instead of bulky air-insulated valve halls, our
approach submerges power modules in a dielectric cooling fluid, eliminating the need for large
cooling and insulation systems, reducing space requirements by over 10.
advanced packaging and bonding techniques we will use innovative sintering and pcb embedded
designs to improve durability and achieve higher power densities.
VIRGINIA POLYTECHNIC INSTITUTE & STATE UNIVERSITY
Applied / lab · DOE mission-applied award.From US DOE, via USAspending · not yet reviewed
- DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation
Scaling monolithic multicores is increasingly constrained by power/thermal limits, yield, and rising manufacturing and testing costs. Chiplet designs address these challenges by partitioning large dies into smaller parts (typically multiple core-complex dies and an I/O die)…
Fundamental research · No laboratory or pilot wording.From arXiv · not yet reviewedPDF
- Conference: Co-designing Networks, Applications, Operating Systems, and Architectures for Large-Scale, AI-driven, Chiplet-rich Systems
Computing systems across all scales – from mobile devices to supercomputers – are increasingly transitioning to chiplet-based architectures and advanced 3D packaging techniques to sustain performance and energy efficiency gains in the wake of the slowing of Moore's Law…
Fundamental research · Research grant.From NSF awards · not yet reviewed
- Formal Foundations for Known Good Reliable Die Screening in Chiplet-Based AI Systems-on-Chip
The rapid growth of chiplet-based artificial intelligence systems-on-chip (SoCs) has exposed a fundamental gap in semiconductor test methodology. Existing Known Good Die (KGD) screening guarantees pre-assembly functional correctness, yet it offers no probabilistic assurance of…
Fundamental research · No laboratory or pilot wording.From arXiv · not yet reviewedPDF
- ThAME: 3D Memory-Enabled Heterogeneous Accelerator for LLM Mixture of Experts
Mixture of Experts (MoE) architectures have emerged as a dominant paradigm for scaling Large Language Models (LLMs). However, MoE inference on conventional hardware is constrained by three fundamental bottlenecks. These encompass the massive memory bandwidth required to fetch…
Fundamental research · No laboratory or pilot wording.From arXiv · not yet reviewedPDF
- Multi-Layer Optical Interconnects and Thermal Management for High-Density Chiplet-Based 3D Heterogeneous Integration
Artificial intelligence, advanced computing, and data-intensive applications require electronic systems that can move substantially larger amounts of data while removing more heat from increasingly compact hardware. Modern computing modules often combine many specialized chips…
Fundamental research · Research grant.From NSF awards · not yet reviewed
- HCRMap: Pressure-Aware Hot-Expert Residency Mapping for 3.5D MoE Chiplet Inference
Mixture-of-Experts (MoE) large language models (LLM) activate only a small number of experts during inference, but token routing introduces persistent expert hotness skew: a small set of hot experts continuously receives most tokens, while the remaining experts are lightly…
Fundamental research · No laboratory or pilot wording.From arXiv · not yet reviewedPDF
- ThermoDSE: A Thermal-Aware and Comprehensive Design Space Exploration for Chiplet-Based DNN Accelerators
Chiplet-based DNN accelerators provide a scalable path to balance performance and yield for modern AI workloads. However, such systems face critical challenges in area and thermal constraints. Design space optimization should jointly consider fine-grained task modeling, chiplet…
Fundamental research · No laboratory or pilot wording.From arXiv · not yet reviewedPDF
- Chiplet3D: Pin- and Thermal-Aware 3D Chiplet Floorplanning via Convolution-Embedded MILP
As traditional Moore's Law scaling slows down, 3D-ICs stack multiple active dies vertically to sustain performance scaling. However, this vertical stacking traps heat inside, making temperature a design concern. Although we can fix thermal issues at different design steps…
Fundamental research · No laboratory or pilot wording.From arXiv · not yet reviewedPDF
- POSE: Phase 1: Parallel Compact Thermal Simulator-Open-Source Ecosystem (PACT-OSE): Building an Ecosystem for Thermal Modeling of Chiplet-based Integration
Managing heat in semiconductor systems is a critical prerequisite to improving computing performance, energy efficiency, and reliability. This requirement is especially important in new chip designs that stack and combine multiple components in compact spaces. Such systems lead…
Applied / lab · Phase I or research-and-innovation award.From NSF awards · not yet reviewed
- Sustainable production line delivering advanced packaging for space missions
To secure EU non-dependence in critical space electronics, the SUPERPACS consortium will build a European supply chain for advanced packaging technologies such as silicon interposer and ultra high-density organic interposers. Reduced line width and spacing (below 5 µm) for…
Pilot / demonstration · Innovation or demonstration award.From OpenAIRE (EU and national funders) · not yet reviewed
- CAREER: Communication Network for Ultra-Large-Scale Chiplet-Based Systems
As the demand for additional compute power and memory continues to increase, the semiconductor industry is shifting towards ultra-large-scale systems capable of providing orders of magnitude greater compute-memory capacity. Applications such as high-performance compute, neural…
University of California-Irvine
Fundamental research · Research grant.From NSF awards · not yet reviewed
- REplaceable Chiplet LInks for Quantum Scaling
Quantum computers could transform industries and society, but to reach their full potential they must scale to millions of qubits. Current superconducting quantum processors (QPUs) are limited by several scaling factors, amongst which fabrication yield and packaging complexity: a…
Pilot / demonstration · Innovation or demonstration award.From OpenAIRE (EU and national funders) · not yet reviewed
- Chiplet-Guard: Proactive Threat Detection for Efficient and Interoperable Chiplet Security
Chiplet-Guard is a pioneering research initiative addressing the security challenges of chiplet-based computing architectures. As the demand for high performance and energy efficiency grows, traditional monolithic System-on-Chip (SoC) designs face physical and economic…
Pilot / demonstration · Innovation or demonstration award.From OpenAIRE (EU and national funders) · not yet reviewed
- The mitre corporation new vision open 2024 award
control number: 3387-2450
title: all-optical chiplets for energy-efficient artificial intelligence
this competitive cooperative agreement for a research and development project entitled, “all-optical chiplets for energy-efficient artificial intelligence” is awarded the mitre corporation under arpa-e foa number de-foa-0003387 (vision open 2024) and control 3387-2450. the purpose of this award is seeks to develop photonic integrated circuits for all-optical, energy-efficient artificial intelligence (ai) in order to address the increasing energy demands of large-scale ai systems.
Applied / lab · DOE mission-applied award.From US DOE, via USAspending · not yet reviewed
- Chiplet-based Hardware Architectures for Software-defined Vehicles
The CHASSIS (Chiplet-based Hardware Architectures for Software-defined Vehicles) project aims to transform the automotive and semiconductor industries by establishing a flexible, open, and collaborative ecosystem for chiplet-based System-on-Chips (SoCs). This initiative supports…
Fundamental research · Research grant.From OpenAIRE (EU and national funders) · not yet reviewed
- Chiplet cOOling solutions for Low-consumption emBedded pRocessing AI at Nanoscale
The COOLBRAIN project embarks on a pioneering journey to unleash the potential of chiplet architecture for embedded systems and smart devices, in particular to use artificial intelligence. Indeed, embedded systems face with a number of challenges when it comes to using processors…
Fundamental research · Research grant.From OpenAIRE (EU and national funders) · not yet reviewed
- Collaborative Research: ASCENT: Optically-Accelerated Heterogeneous AI Computing Chiplet (OCTANT)
Nontechnical Description The rapid rise of generative artificial intelligence (AI) has ushered society into a new era of supercomputing-driven data exploration. This tipping point is intensifying the gap between the exploding size of AI models and the limited computing throughput…
Regents of the University of Michigan - Ann Arbor
Fundamental research · Research grant.From NSF awards · not yet reviewedalso at nsf.gov
- DESC: Type I: Water- and Carbon-Aware Design of Chiplet-based Systems with Reconfigurability for AI in Datacenters
As artificial intelligence (AI) applications become increasingly central to our daily lives, the datacenters that serve these applications are growing rapidly. However, this growth comes with a significant environmental cost. These datacenters rely on computer chips whose design…
Fundamental research · Research grant.From NSF awards · not yet reviewed
- SHF: CSR: Medium: Practical and Efficient Accelerators with High-Frequency Chiplets
Modern computer chip design faces a critical bottleneck: creating high-performance hardware accelerators requires countless manual iterations and expert-years of development time. This project addresses a national priority by developing automated Artificial Intelligence (AI)…
University of California-Santa Cruz
Fundamental research · Research grant.From NSF awards · not yet reviewed
- DESC: Type II: CHIPLETS360: Datacenter Optimization Through Whole-stack Novel Accounting, Design, Reuse, and Heterogeneous Provisioning of CHIPLETS
Data centers play a vital role in modern computing, supporting everything from personal internet use to a wide range of industries. As demand for computing power grows, next-generation data centers must be designed with smarter, more precise integration of technologies to improve…
Fundamental research · Research grant.From NSF awards · not yet reviewed
- PFI-TT: Developing Advanced Thermal Packaging Materials for the Semiconductor Industry Using Hexagonal Boron Nitride Nanosheets
This Partnerships for Innovation - Technology Translation (PFI-TT) project seeks to improve the chip packaging industry. Semiconductors are the foundation for top U.S. exports such as artificial intelligence, medical devices, and transportation vehicles. Optimizing thermal…
Fundamental research · Research grant.From NSF awards · not yet reviewed
- STTR Phase II: Miniature Precision Stage for High Throughput Hybrid Bonding
The broader/commercial impact of this Small Business Technology Transfer (STTR) Phase II project is to develop a small form-factor precision stage to enable the high-volume manufacturing of next generation high-performance computing devices utilizing 3D stacked chiplets…
Pilot / demonstration · SBIR/STTR Phase II award.From NSF awards · not yet reviewed
- CAREER: Optimizing the Next Frontiers of Chiplet-based Designs in Advanced Packaging
Modern Artificial Intelligence (AI) workloads demand computing systems with large silicon areas to sustain throughput and performance. However, manufacturing costs, yield limitations at advanced tech nodes, and die sizes reaching the reticle limit restrain us from achieving this…
Fundamental research · Research grant.From NSF awards · not yet reviewed
- Advanced Packaging and Heterogeneous Integration for Electronic Components and Systems Pilot Line
As a contribution to the EU Chips Act, the Research Fab Microelectronics Germany (FMD) proposes an Advanced Packaging and Heterogeneous Integration for Electronic Components and Systems Pilot Line (APECS-PL), which combines the generation of globally competitive high technology…
Pilot / demonstration · Innovation or demonstration award.From OpenAIRE (EU and national funders) · not yet reviewed
- EPSCoR Research Fellows: NSF: Heterogeneous Integration of Wide Bandgap Semiconductor Chips for High Temperature Applications
Commercial semiconductor chips and their packages are designed to work at temperatures up to 250℃. They will fail to work after a few hours at temperatures above this threshold. In recent years, research has been conducted to develop special chips made of different semiconductor…
Regents of the University of Idaho
Fundamental research · Research grant.From NSF awards · not yet reviewed
- FuSe2 Topic 2: Heterogenous Integration of Wide-Bandgap Microelectronics and Power Electronics for Efficient Power Delivery to AI Processors in Data Centers
Nontechnical description: Data centers consume ~2% of the global electricity. However, the efficiency of power delivery in data centers is only 70~80%. This efficiency is largely limited by the resistive loss on the lateral power delivery board of the 48-to-1/0.8 V point-of-load…
Virginia Polytechnic Institute and State University
Fundamental research · Research grant.From NSF awards · not yet reviewed
- SHF/FET: 2.5D/3D Heterogeneous Integration of In-Pixel and Near-Pixel Compute Chiplets
Personal computers and mobile phones have been the primary platforms for interaction with the digital world, pervading every corner of the modern society in the past few decades. Augmented Reality/Virtual Reality (AR/VR) is regarded as the general human-oriented computing…
Georgia Tech Research Corporation
Fundamental research · Research grant.From NSF awards · not yet reviewed
- Large-scale photonic chiplet Taichi empowers 160-TOPS/W artificial general intelligence
The pursuit of artificial general intelligence (AGI) continuously demands higher computing performance. Despite the superior processing speed and efficiency of integrated photonic circuits, their capacity and scalability are restricted by unavoidable errors, such that only simple…
Tsinghua–Berkeley Shenzhen InstituteNational Engineering Research Center for Information Technology in AgricultureTsinghua Shenzhen International Graduate SchoolBeijing National Research Center for Information Science and TechnologyTsinghua University
Fundamental research · No laboratory or pilot wording.From OpenAlex · not yet reviewedDOI
- Collaborative Research: SHF: Medium: Tiny Chiplets for Big AI: A Reconfigurable-On-Package System
As monolithic chips reach their technological and practical limits, the integration of chiplets is emerging as the primary mechanism to continuously scale up processor performance, improve power efficiency, enhance IP reuse at low cost, and expedite time-to-market. This new…
University of Minnesota-Twin Cities
Fundamental research · Research grant.From NSF awards · not yet reviewedalso at nsf.gov
- STTR Phase I: Microhydraulic Actuator for High-Accuracy, High-Speed Position Stages
The broader impact/commercial potential of this Small Business Technology Transfer (STTR) Phase I project is to develop the key technology to enable the building of high-precision, high-throughput, semiconductor advanced packaging systems to enable broad adoption of the 3D…
Pilot / demonstration · Innovation or demonstration award.From NSF awards · not yet reviewed
- Linking microbial contamination to food spoilage and food waste: the role of smart packaging, spoilage risk assessments, and date labeling
Ensuring a safe and adequate food supply is a cornerstone of human health and food security. However, a significant portion of the food produced for human consumption is wasted annually on a global scale. Reducing harvest and postharvest food waste, waste during food processing…
University of Maryland, College ParkUniversity of Maryland ExtensionCenter for Food Safety and Applied Nutrition
Fundamental research · No laboratory or pilot wording.From OpenAlex · not yet reviewedDOIPDF
- Challenges and prospects for advanced packaging
In the post-Moore era, advanced packaging is becoming more critical to meet the everlasting demands of electronic products with smaller size, more powerful performance and lower cost. In this paper, developments in advanced packaging have been discussed, such as 3D IC packaging…
Wuhan UniversityZhuhai Fudan Innovation Research InstituteGeorgia Institute of Technology
Fundamental research · No laboratory or pilot wording.From OpenAlex · not yet reviewedDOI
- Universal Chiplet Interconnect Express (UCIe): An Open Industry Standard for Innovations With Chiplets at Package Level
Universal Chiplet Interconnect Express (UCIe) is an open industry standard interconnect for developing an open chiplet ecosystem, where chiplets from any supplier can be packaged anywhere in an interoperable manner. This article delves into the architectural, circuit, channel…
Intel (United States)Intel in the directoryINTC USvia Intel
Fundamental research · No laboratory or pilot wording.From OpenAlex · not yet reviewedDOI
- (PITCH) advanced PackagIng Test probe Card laser microHoles
More-than-Moore's law increasingly drives advanced packaging technologies and probecard testing developments for semiconductor wafer-level testing. Sophisticated custom-made probecards for each IC design are used to establish Known-Good-Die before packaging and hence critical …
Fundamental research · Research grant.From OpenAIRE (EU and national funders) · not yet reviewed
- Reconfigurable heterogeneous integration using stackable chips with embedded artificial intelligence
Massachusetts Institute of TechnologyKorea Institute of Science and TechnologyGwangju Institute of Science and TechnologyUniversity of CincinnatiJeonbuk National University+7 more
Fundamental research · No laboratory or pilot wording.From OpenAlex · not yet reviewedDOI
- Recent Advances and Trends in Advanced Packaging
In this study, advanced packaging is defined. The kinds of advanced packaging are ranked based on their interconnect density and electrical performance, and are grouped into 2-D, 2.1-D, 2.3-D, 2.5-D, and 3-D IC integration, which will be presented and discussed. Chiplet design…
Fundamental research · No laboratory or pilot wording.From OpenAlex · not yet reviewedDOI
- Recent trends in nanotechnology applications of bio-based packaging
Nanotechnology has reached to almost every sector and amazed the world by offering various potential applications in these sectors. Since nanostructure materials have been known for their unique physical and chemical properties and enhanced performance, hence preferred over their…
Central University of South BiharMahatma Gandhi Central University
Fundamental research · No laboratory or pilot wording.From OpenAlex · not yet reviewedDOIPDF