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AI & compute · Semiconductors

High-numerical-aperture EUV

The next generation of the machine that prints chip patterns, with larger optics that resolve finer features in one pass.

Readiness · Estimate, not a measurementPast development: ASML says Intel Foundry entered high-volume manufacturing on High-NA-patterned layers in 2026, at yields matching the previous generation. This row said "not yet volume production" until the source was read.By Substrata, open to challenge · 2026-09-15Supporting source → — Qualified and entering production (Reaching production)Report an error on GitHub

01What it would relieve

  • Leading-edge foundry capacityHow this is computedSum of four judged scores, each 0–3: concentration + substitution + lead time + inelasticity.Method →Code →

    Printing finer features in a single exposure removes multi-pass steps, so each machine produces more finished wafers.

02How far off it is

judged 2026-09-15

8 / 9Qualified and entering production

Past development: ASML says Intel Foundry entered high-volume manufacturing on High-NA-patterned layers in 2026, at yields matching the previous generation. This row said "not yet volume production" until the source was read.

Source ↗

03What to watch for

A product shipping in volume from a high-NA layer.

04Who and what it would touch

each join carries its own evidence
Companies that make it today

sourced

Other science aimed at it
Nothing else is on record yet.
Who could fund relief
No funder is on record yet.
Where it comes from

directory join, not a sourced finding

What it holds up

the project's own model, not a measurement

05What this holds up

3 loops
  • Software scaffoldone turn: Minutes

    would relieve Leading-edge foundry capacity, which gates it.

    Worst judgement on this loop: How this is computedThe highest severity score among the bottlenecks recorded as gates on the loop.Method →Code →, judged 2026-09-15 · this join is source-backed readiness judgement

  • Firmware and programmable logicone turn: Minutes to hours

    would relieve Leading-edge foundry capacity, which gates it.

    Worst judgement on this loop: How this is computedThe highest severity score among the bottlenecks recorded as gates on the loop.Method →Code →, judged 2026-09-15 · this join is source-backed readiness judgement

  • Frontier training runone turn: Weeks to months

    would relieve Leading-edge foundry capacity, which gates it.

    Worst judgement on this loop: How this is computedThe highest severity score among the bottlenecks recorded as gates on the loop.Method →Code →, judged 2026-09-15 · this join is source-backed readiness judgement

A loop is one design, build and measure turn. Severity is a dated judgement on a 0–12 scale, not a measurement, and the judgements are not added together — the figure shown is the worst single one.

Discussion

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