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Company · TW KR US

Leading-edge foundry capacity

Factories that can make chips at the newest generation. A handful exist, and the leader spends tens of billions of dollars a year adding more.

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Severity
How this is computedSum of four judged scores, each 0–3: concentration + substitution + lead time + inelasticity.Method →Code →
How hard it binds, 0 to 12
When it bites
Now
judged 2026-09-15
Evidence
Verified
3 maker rows

AI & computeAdvanced manufacturingSemiconductorsWork on it: roles and trainingReport an error on GitHub

01Key numbers

dated, each linked to its source

What the text on this page claims, and the number behind it

  • New capacity is a commitment of tens of billions of dollars a year Measured

    TSMC capital spending, as it reported and guided it. "Multi-year" was dropped: no source states how long a new leading-edge fab takes.

    TSMC capital expenditures: SourcedTSMC 4Q25 earnings call transcriptOpen the source → USD bn, Q4 2025TSMC capital budget guidance: SourcedTSMC 4Q25 earnings release (SEC Form 6-K exhibit)Open the source → USD bn, 2026

2 (Computed: Count of dated values in a series, or of series matching the filters, across the committed corpus and the official statistics fetched on schedule.) more series on this bottleneck
  • Capacity · company: TSMCTSMC capital expenditures (NT$)SourcedTSMC Form 20-F FY2025 · 2025Open the source → TWD bn2025How this is computedThe latest value in a series minus the value before it, divided by the earlier value, same series and unit.956.007 (2024) → 1,272.411 (2025).Method →Code → vs 2024 · loosens
    TSMC capital expenditures (NT$), TWD bn, 2020 to 2025. Every value is listed in the table below.
    500
    1,000
    1,500
    507.239 TWD bn2020TSMC Form 20-F FY2022 ↗839.196 TWD bn2021TSMC Form 20-F FY2022 ↗1,082.672 TWD bn2022TSMC Form 20-F FY2022 ↗949.817 TWD bn2023TSMC Form 20-F FY2025 ↗956.007 TWD bn2024TSMC Form 20-F FY2025 ↗1,272.411 TWD bn2025TSMC Form 20-F FY2025 ↗
    PeriodValueSource
    2025SourcedTSMC Form 20-F FY2025 · 2026-04-16Open the source → TWD bnTSMC Form 20-F FY2025 ↗ primaryOur capital expenditures in 2023 , 2024 and 2025 were NT$ 949,817 million, NT$ 956,007 million and NT$ 1,272,411 millionStated in NT$ million
    2024SourcedTSMC Form 20-F FY2025 · 2026-04-16Open the source → TWD bnTSMC Form 20-F FY2025 ↗ primaryOur capital expenditures in 2023 , 2024 and 2025 were NT$ 949,817 million, NT$ 956,007 million and NT$ 1,272,411 millionStated in NT$ million
    2023SourcedTSMC Form 20-F FY2025 · 2026-04-16Open the source → TWD bnTSMC Form 20-F FY2025 ↗ primaryOur capital expenditures in 2023 , 2024 and 2025 were NT$ 949,817 million, NT$ 956,007 million and NT$ 1,272,411 millionStated in NT$ million
    2022SourcedTSMC Form 20-F FY2022 · 2023-04-20Open the source → TWD bnTSMC Form 20-F FY2022 ↗ primaryOur capital expenditures in 2020, 2021 and 2022 were NT$507,239 million, NT$839,196 million and NT$1,082,672 millionStated in NT$ million
    2021SourcedTSMC Form 20-F FY2022 · 2023-04-20Open the source → TWD bnTSMC Form 20-F FY2022 ↗ primaryOur capital expenditures in 2020, 2021 and 2022 were NT$507,239 million, NT$839,196 million and NT$1,082,672 millionStated in NT$ million
    2020SourcedTSMC Form 20-F FY2022 · 2023-04-20Open the source → TWD bnTSMC Form 20-F FY2022 ↗ primaryOur capital expenditures in 2020, 2021 and 2022 were NT$507,239 million, NT$839,196 million and NT$1,082,672 millionStated in NT$ million

    Read from the sources Read from the source by an agent; quote matched mechanically against the fetched page; not yet reviewed by a person, 2026-09-24. Each value links the page it came from and quotes the sentence that carries it.

    Series pageDownload CSV

  • Other · company: TSMCTSMC 2nm share of wafer revenueSourcedTSMC 2Q26 earnings release (SEC Form 6-K exhibit) · Q2 2026Open the source → %Q2 2026
    PeriodValueSource
    Q2 2026SourcedTSMC 2Q26 earnings release (SEC Form 6-K exhibit) · 2026-07-16Open the source → %TSMC 2Q26 earnings release (SEC Form 6-K exhibit) ↗ primaryIn the second quarter, shipments of 2-nanometer accounted for 3% of total wafer revenue; 3-nanometer accounted for 30%; 5-nanometer accounted for 33%; and 7-nanometer accounted for 11%.

    Read from the sources Read from the source by an agent; quote matched mechanically against the fetched page; not yet reviewed by a person, 2026-09-24. Each value links the page it came from and quotes the sentence that carries it.

    Series pageDownload CSV

Every series on every bottleneck — filter, compare and download.

02Why it holds things up

A handful of fabs can run the newest node at volume. New capacity is a commitment of tens of billions of dollars a year, so the supply curve cannot answer a demand shock quickly.

Part of the process · Compute, which takes quarters to years to loosen once somebody decides to.

03Severity

judged 2026-09-15 · a judgement, not a measurement

How this is computedSum of four judged scores, each 0–3: concentration + substitution + lead time + inelasticity.Method →Code → / 12

How few suppliers qualify
Estimate, not a measurementA handful of fabs at the newest node; new capacity costs tens of billions of dollars a year.By Substrata, open to challenge · 2026-09-15 / 3
How hard to replace
Estimate, not a measurementA handful of fabs at the newest node; new capacity costs tens of billions of dollars a year.By Substrata, open to challenge · 2026-09-15 / 3
Decision to new capacity
Estimate, not a measurementA handful of fabs at the newest node; new capacity costs tens of billions of dollars a year.By Substrata, open to challenge · 2026-09-15 / 3
Can the buyer walk away
Estimate, not a measurementA handful of fabs at the newest node; new capacity costs tens of billions of dollars a year.By Substrata, open to challenge · 2026-09-15 / 3

A handful of fabs at the newest node; new capacity costs tens of billions of dollars a year.

04Who makes it

3 verified of 3 rows
OrganisationStepEvidence
TSMC2330 TTRuns the capacityVerified source ↗
Samsung Foundry005930 KSvia Samsung ElectronicsRuns the capacityVerified source ↗
Intel FoundryINTC USvia IntelRuns the capacityVerified source ↗

05What it rests on, and what rests on it

each row quotes the page it rests on

Depends on

  • EUV lithography scanners
    “EUV technology enables TSMC to keep driving chip scaling as the shorter wavelength of EUV light is better able to print the nanometer-scale features of advanced technology designs.”

    pr.tsmc.com · primary source

  • Photoresist formulation
    “We continue to research and develop EUV resists with absorption wavelengths of 13.5nm, with a proven track record in mass production lines.”

    tok-pr.com · primary source · A resist maker describing its own product in mass production; it does not name a fab.

  • 300 mm prime silicon wafers
    “300 mm Non-memory chip / MPU / CIS / Logic (Driver IC)”

    sksiltron.com · primary source · A wafer maker’s product table: 300 mm wafers go to logic. It does not name a node.

  • Neon, excimer laser grade
    “Their highly pure inert neon gas is needed as a buffer for lasers used during the chip fabrication process.”

    theregister.com · secondary source · Chip fabrication in general, not the leading edge only.

  • Liquid helium (He-4)
    “Among the latest geopolitical uncertainties for the industry is a shortage of helium that could slow global production.”

    dw.com · secondary source · Chip production in general, not the leading edge only.

Depended on by

  • Advanced packaging capacity
    “so that various chiplets such as SoC and and high bandwidth memory (HBM) can be placed on it”

    investor.tsmc.com · primary source · TSMC’s 2022 annual report on the CoWoS interposer. The SoC dies are the logic side.

  • NVIDIA
    “We utilize foundries, such as Taiwan Semiconductor Manufacturing Company Limited, or TSMC, and Samsung Electronics Co., Ltd., or Samsung, to produce our semiconductor wafers.”

    sec.gov · primary source · The filing names the foundries, not the node.

  • AMD
    “We utilize Taiwan Semiconductor Manufacturing Company Limited (TSMC) for the production of wafers for our HPC, FPGA and adaptive SoC products”

    sec.gov · primary source · The filing names the foundry, not the node.

  • Broadcom
    “The majority of our front-end wafer manufacturing operations is outsourced to external foundries, including Taiwan Semiconductor Manufacturing Company Limited ("TSMC").”

    sec.gov · primary source · The filing names the foundry, not the node.

  • Microsoft
    “Fabricated on TSMC’s cutting-edge 3-nanometer process, each Maia 200 chip contains over 140 billion transistors”

    blogs.microsoft.com · primary source · Microsoft’s own Maia 200 accelerator only, not the GPUs it buys.

  • Amazon Web Services
    “Amazon EC2 Trn3 UltraServers powered by AWS's first 3nm AI chip help organizations of all sizes run their most ambitious AI training and inference workloads.”

    aboutamazon.com · primary source · Names a 3 nm chip, which only leading-edge foundries make; does not name the foundry.

  • CoreWeave
    “For example, NVIDIA relies on suppliers such as Taiwan Semiconductor Manufacturing Company for semiconductor fabrication and other manufacturers for compute and networking components.”

    sec.gov · primary source · Through NVIDIA, its GPU supplier. CoreWeave buys no wafers itself.

  • Marvell
    “Most of our products are manufactured by third-party foundries located in Taiwan, and other sources are located in China, Germany, South Korea, Singapore and the United States.”

    sec.gov · primary source · Fiscal 2026 10-K. Names Taiwan, not TSMC and not the node.

Sold into by

  • Applied Materials
    “Our Semiconductor Systems sales are to customers that serve the following markets: foundry, logic and other; dynamic random access memory (DRAM); and flash memory (NAND).”

    sec.gov · primary source · Names the market (foundry and logic), not the leading edge only.

  • Lam Research
    “Our customer base includes leading semiconductor memory, foundry, and integrated device manufacturers ("IDMs") that make products such as non-volatile memory ("NVM"), dynamic random-access memory ("DRAM"), and logic devices.”

    sec.gov · primary source · Names the market (foundry, logic), not the leading edge only.

  • KLA
    “For the fiscal years ended June 30, 2026, 2025 and 2024, the following customers each accounted for more than 10% of total revenues, primarily in the Semiconductor Process Control segment:”

    sec.gov · primary source · The table under this sentence names Taiwan Semiconductor Manufacturing Company Limited in all three years.

  • Tokyo Electron
    “In the Account Sales Division, we receive and leverage next-generation technology needs shared by major semiconductor manufacturers such as those in memory, logic, and foundry businesses driving current momentum in the AI device market”

    tel.com · primary source · Integrated Report 2026. Its table of major customers names Samsung Electronics and TSMC.

  • ASM International
    “The leading-edge logic/foundry market was the main growth driver for ASM, on the back of 2nm investments.”

    asm.com · primary source · Annual Report 2025. Customers are not named.

A recorded dependency is a sentence, not a share, a volume or a contract. Walk it on a portfolio →

06Rules that govern it

All policy →

07What would remove it

  • High-numerical-aperture EUVEstimate, not a measurementPast development: ASML says Intel Foundry entered high-volume manufacturing on High-NA-patterned layers in 2026, at yields matching the previous generation. This row said "not yet volume production" until the source was read.By Substrata, open to challenge · 2026-09-15Supporting source → · Qualified and entering production

    Printing finer features in a single exposure removes multi-pass steps, so each machine produces more finished wafers.

All science →

08Science pipeline

54 papers, preprints and grants collected, unreviewed
  1. Research47 (Computed: Items per stage = papers, preprints and grants collected for the bottleneck whose relevance score is 2 or more, placed on a stage by the rule in lib/science.ts; judgements are counted separately.)+2 (Computed: Items first collected in the last 7 days whose publication or award date is within the last 30 days.) new
  2. Lab6 (Computed: Items per stage = papers, preprints and grants collected for the bottleneck whose relevance score is 2 or more, placed on a stage by the rule in lib/science.ts; judgements are counted separately.)+1 (Computed: Items first collected in the last 7 days whose publication or award date is within the last 30 days.) new
  3. Pilot1 (Computed: Items per stage = papers, preprints and grants collected for the bottleneck whose relevance score is 2 or more, placed on a stage by the rule in lib/science.ts; judgements are counted separately.)
  4. Early0 (Computed: Items per stage = papers, preprints and grants collected for the bottleneck whose relevance score is 2 or more, placed on a stage by the rule in lib/science.ts; judgements are counted separately.)
  5. Scale0 (Computed: Items per stage = papers, preprints and grants collected for the bottleneck whose relevance score is 2 or more, placed on a stage by the rule in lib/science.ts; judgements are counted separately.)

judged, with a citation claimed, no citationNumber: papers, preprints and grants the feeds collected — unreviewed

The full pipeline, by stage →

09What has happened

1 dated
  1. 2026-07-30
    LoosensCapacityUS KR

    Samsung brings its first Taylor, Texas fab online and will start a second by year end, warning the shortage runs to 2028.

    WhoSamsung Foundry

    koreaherald.com ↗secondary source

    The sentence that says so

    “Samsung Electronics is accelerating its US chip expansion, bringing its first Taylor, Texas, foundry online this year and starting construction of a second fab by year-end.”

All events →

10What this holds up

3 loops
  • Software scaffoldone turn: Minutes

    Worst judgement on this loop: How this is computedThe highest severity score among the bottlenecks recorded as gates on the loop.Method →Code →, judged 2026-09-15

  • Firmware and programmable logicone turn: Minutes to hours

    Worst judgement on this loop: How this is computedThe highest severity score among the bottlenecks recorded as gates on the loop.Method →Code →, judged 2026-09-15

  • Frontier training runone turn: Weeks to months

    Worst judgement on this loop: How this is computedThe highest severity score among the bottlenecks recorded as gates on the loop.Method →Code →, judged 2026-09-15

A loop is one design, build and measure turn. Severity is a dated judgement on a 0–12 scale, not a measurement, and the judgements are not added together — the figure shown is the worst single one.

Discussion

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